Methods for preventing oxidation damage during finfet fabrication

ABSTRACT

Embodiments of the present invention provide improved methods for fabricating field effect transistors such as finFETs. Stressor regions are used to increase carrier mobility. However, subsequent processes such as deposition of flowable oxide and annealing can damage the stressor regions, diminishing the amount of stress that is induced. Embodiments of the present invention provide a protective layer of silicon or silicon oxide over the stressor regions prior to the flowable oxide deposition and anneal.

FIELD OF THE INVENTION

The present invention relates generally to semiconductor fabricationand, more particularly, to methods for preventing oxidation damageduring finFET fabrication.

BACKGROUND

FinFETs (Fin field-effect-transistors) are a technology which allowssmaller and higher performance devices. FinFET structures comprisenarrow isolated bars of silicon (fins) with a gate(s) on the top and thesides of the fin. With the continuing trend towards miniaturization ofintegrated circuits (ICs), there is a need for transistors having higherperformance. Furthermore, with large quantities of ICs being produced,product yield becomes increasingly important. It is therefore desirableto have improved methods of fabrication for finFET devices.

SUMMARY OF THE INVENTION

In a first aspect, embodiments of the present invention provide a methodof forming a semiconductor structure, comprising: forming a plurality ofstressor regions adjacent to a gate; forming a contact etch stoppinglayer on the gate and plurality of stressor regions; removing thecontact etch stopping layer from a top portion of the gate and pluralityof stressor regions; depositing a silicon layer on the gate andplurality of stressor regions; depositing a flowable oxide on theplurality of stressor regions; and performing an anneal on thesemiconductor structure.

In a second aspect, embodiments of the present invention provide amethod of forming a semiconductor structure, comprising: forming aplurality of stressor regions adjacent to a gate; forming a contact etchstopping layer on the gate and plurality of stressor regions; removingthe contact etch stopping layer from a top portion of the gate andplurality of stressor regions; depositing a silicon oxide layer on thegate and plurality of stressor regions; depositing a flowable oxide onthe plurality of stressor regions; and performing an anneal on thesemiconductor structure.

In a third aspect, embodiments of the present invention provide a methodof forming a semiconductor structure, comprising: forming a plurality ofstressor regions adjacent to a gate; forming a contact etch stoppinglayer of silicon nitride on the gate and plurality of stressor regionsusing an atomic layer deposition process; removing the contact etchstopping layer from a top portion of the gate and plurality of stressorregions; depositing a silicon oxide layer on the gate and plurality ofstressor regions; depositing a flowable oxide on the plurality ofstressor regions; and performing an anneal on the semiconductorstructure.

BRIEF DESCRIPTION OF THE DRAWINGS

Certain elements in some of the figures may be omitted, or illustratednot-to-scale, for illustrative clarity. The cross-sectional views may bein the form of “slices”, or “near-sighted” cross-sectional views,omitting certain background lines which would otherwise be visible in a“true” cross-sectional view, for illustrative clarity. Furthermore, forclarity, some reference numbers may be omitted in certain drawings.

Often, similar elements may be referred to by similar numbers in variousfigures (FIGs) of the drawing, in which case typically the last twosignificant digits may be the same, the most significant digit being thenumber of the drawing figure (FIG.).

Features of this invention will be more readily understood from thefollowing detailed description of the various aspects of the inventiontaken in conjunction with the accompanying drawings in which:

FIG. 1A is a semiconductor structure at a starting point forillustrative embodiments;

FIG. 1B is a top-down view of a semiconductor structure at a startingpoint for illustrative embodiments;

FIG. 2 is a semiconductor structure after a subsequent step of removinga portion of the contact etch stop layer, in accordance withillustrative embodiments;

FIG. 3 is a semiconductor structure after a subsequent step ofdepositing an oxide layer, in accordance with illustrative embodiments;

FIG. 4 is a semiconductor structure at a starting point for alternativeillustrative embodiments;

FIG. 5 is a semiconductor structure after a subsequent step ofdepositing a silicon layer, in accordance with illustrative embodiments;

FIG. 6 is a semiconductor structure after subsequent steps of depositinga flowable oxide and performing an anneal, in accordance withillustrative embodiments;

FIG. 7 is a flowchart indicating process steps for illustrativeembodiments; and

FIG. 8 is a flowchart indicating process steps for alternativeillustrative embodiments.

DETAILED DESCRIPTION

Exemplary embodiments will now be described more fully herein withreference to the accompanying drawings, in which exemplary embodimentsare shown. Embodiments of the present invention provide improved methodsfor fabricating field effect transistors such as finFETs. Stressorregions are used to increase carrier mobility. However, subsequentprocesses such as deposition of flowable oxide and annealing can damagethe stressor regions, diminishing the amount of stress that is induced.Embodiments of the present invention provide a protective layer ofsilicon or silicon oxide over the stressor regions prior to the flowableoxide deposition and anneal.

It will be appreciated that this disclosure may be embodied in manydifferent forms and should not be construed as limited to the exemplaryembodiments set forth herein. Rather, these exemplary embodiments areprovided so that this disclosure will be thorough and complete and willfully convey the scope of this disclosure to those skilled in the art.The terminology used herein is for the purpose of describing particularembodiments only and is not intended to be limiting of this disclosure.For example, as used herein, the singular forms “a”, “an”, and “the” areintended to include the plural forms as well, unless the context clearlyindicates otherwise. Furthermore, the use of the terms “a”, “an”, etc.,do not denote a limitation of quantity, but rather denote the presenceof at least one of the referenced items. It will be further understoodthat the terms “comprises” and/or “comprising”, or “includes” and/or“including”, when used in this specification, specify the presence ofstated features, regions, integers, steps, operations, elements, and/orcomponents, but do not preclude the presence or addition of one or moreother features, regions, integers, steps, operations, elements,components, and/or groups thereof.

Reference throughout this specification to “one embodiment,” “anembodiment,” “embodiments,” “exemplary embodiments,” or similar languagemeans that a particular feature, structure, or characteristic describedin connection with the embodiment is included in at least one embodimentof the present invention. Thus, appearances of the phrases “in oneembodiment,” “in an embodiment,” “in embodiments” and similar languagethroughout this specification may, but do not necessarily, all refer tothe same embodiment.

The terms “overlying” or “atop”, “positioned on” or “positioned atop”,“underlying”, “beneath” or “below” mean that a first element, such as afirst structure (e.g., a first layer), is present on a second element,such as a second structure (e.g. a second layer), wherein interveningelements, such as an interface structure (e.g. interface layer), may bepresent between the first element and the second element.

FIG. 1A is a semiconductor structure 100 at a starting point forillustrative embodiments. Structure 100 comprises a substrate 102, whichmay be a silicon substrate, such as a bulk silicon substrate orsilicon-on-insulator (SOI) substrate. A shallow trench isolation (STI)layer 104 is formed on substrate 102. STI layer 104 may be comprised ofoxide, such as silicon oxide. Stressor regions 108, 110, and 112 areformed adjacent to gate 106, which may be comprised of polysilicon. Gate106 may be a dummy gate that is later replaced with a metal gate duringa replacement metal gate (RMG) process. FIG. 1B shows a top-down view,indicating the positioning of the stressor regions 108, 110, and 112 asadjacent to gate 106. In this exemplary embodiment, stressor regions 108and 110 are N-type stressor regions, and may be comprised of siliconphosphorous (SiP). Stressor region 112 is comprised of silicon germanium(SiGe). A pad nitride layer 114 is formed over gate 106. In embodiments,pad nitride layer 114 is comprised of silicon nitride (SiN). Spacerlayer 116 is formed adjacent to gate 106. In embodiments, spacer layer116 may be comprised of nitride, such as silicon nitride. A smallportion of cap oxide 120 is disposed on pad nitride layer 114. Thespacer layer 116 may be disposed on the cap oxide 120 and on a portionof the pad nitride layer 114. The portion of spacer layer disposed oncap oxide 120 is referred to as a N/P overlap bump, which may beresulting from separate processing for PFETs and NFETs. A second spacer122 may be formed over the P-type stressor region 112 to protect itduring formation of N-type stressor regions 108 and 110. Contact etchstopping layer (CESL) 118 is deposited over the structure, includingover the gate and over the stressor regions 108, 110, and 112. In someembodiments, CESL 118 may be deposited using an atomic layer depositionprocess.

FIG. 2 shows semiconductor structure 100 after a subsequent process stepof removing a portion of the CESL 118 in accordance with illustrativeembodiments. In embodiments, the removing of a portion of the CESL 118may be performed with an anisotropic etch process, or with a wet etchprocess. As shown in FIG. 2, the CESL 118 is removed from the top of thepad nitride layer 114, and CESL 118 is also removed from a top portionof stressor regions 108, 110, and 112. A portion of the second spacer122 is also removed from the top portion of P-type stressor region 112.

FIG. 3 shows semiconductor structure 100 after a subsequent step ofdepositing an oxide layer 124, in accordance with illustrativeembodiments. In embodiments, the oxide layer 124 may be a silicon oxidelayer. In some embodiments, the oxide layer 124 may have a thickness T1ranging from about 50 angstroms to about 150 angstroms. In embodiments,the oxide layer 124 may be deposited by performing an In-situ RadicalAssisted Deposition (IRAD) process. The oxide layer 124 serves toprotect stressor regions 108, 110, and 112 during subsequent processsteps, such as annealing, and deposition of flowable oxide. The flowableoxide may be used as an insulator region between the stressor regions108, 110, and 112. From this point forward, industry standard techniquesmay be used to complete fabrication of the integrated circuit. Thesesteps may include additional interlayer dielectrics, contacts,metallization layers, and packaging, among others.

FIG. 4 is a semiconductor structure 200 at a starting point foralternative illustrative embodiments. Structure 200 comprises asubstrate 202, which may be a silicon substrate, such as a bulk siliconsubstrate or silicon-on-insulator (SOI) substrate. A shallow trenchisolation (STI) layer 204 is formed on substrate 202. STI layer 204 maybe comprised of oxide, such as silicon oxide. Stressor regions 208, 210,and 212 are formed adjacent (similar to as shown in FIG. 1B) to gate206, which may be comprised of polysilicon. In this exemplaryembodiment, stressor regions 208 and 210 are N-type stressor regions,and may be comprised of silicon phosphorous (SiP). Stressor region 212is comprised of silicon germanium (SiGe). A pad nitride layer 214 isformed over gate 206. In embodiments, pad nitride layer 214 is comprisedof silicon nitride (SiN). Spacer layer 216 is formed adjacent to gate206. In embodiments, spacer layer 216 may be comprised of nitride, suchas silicon nitride. A small portion of cap oxide 220 is disposed on padnitride layer 214. The spacer layer 216 may be disposed on the cap oxide220 and on a portion of the pad nitride layer 214. The portion of spacerlayer disposed on cap oxide 220 is referred to as a N/P overlap bump,which may be resulting from separate processing for PFETs and NFETs. Asecond spacer 222 may be formed over the P-type stressor region 212 toprotect it during formation of N-type stressor regions 208 and 210.

FIG. 5 shows semiconductor structure 200 after a subsequent step ofdepositing a silicon layer 230, in accordance with illustrativeembodiments. Silicon layer 230 may be deposited via a chemical vapordeposition (CVD) process. In embodiments, silicon layer 230 may have athickness T2 ranging from about 10 angstroms to about 50 angstroms. Thesilicon layer 230 serves to protect stressor regions 208, 210, and 212during subsequent process steps, such as annealing, and deposition offlowable oxide.

FIG. 6 shows semiconductor structure 200 after subsequent steps ofdepositing a flowable oxide 234 and performing an anneal, in accordancewith illustrative embodiments. The flowable oxide 234 covers thesemiconductor structure 200, but is shown transparent so that otherdetails can remain visible in FIG. 6. Flowable oxide 234 may bedeposited via a flowable chemical vapor deposition (FCVD) process.Following the FCVD process, an anneal, such as a steam anneal, isperformed. In some embodiments, the anneal may be performed for aduration ranging from about 20 minutes to about 5 hours. In someembodiments, the duration may range from about 90 minutes to about 150minutes. In some embodiments, the anneal may be performed at a processtemperature ranging from about 100 degrees Celsius to about 700 degreesCelsius. In some embodiments, the anneal may be performed at a processtemperature ranging from about 400 degrees Celsius to about 600 degreesCelsius. The FCVD process and anneal can serve to oxidize silicon layer230 (FIG. 5), converting it to a silicon oxide layer 232 as shown inFIG. 6. In this way, the stressor regions 208, 210, and 212 remainintact, and do not get oxidized themselves. If the stressor regions 208,210, and 212 were to get oxidized, it would reduce the amount ofmaterial able to contribute to the stress, and hence, would adverselyaffect the device performance.

FIG. 7 is a flowchart 700 indicating process steps for illustrativeembodiments. In process step 750, stressor regions are formed. Thestressor regions may include formation of regions of silicon germanium(SiGe), silicon phosphorous (SiP), and silicon carbon phosphorous(SiCP). The stressor regions may be formed via an epitaxial process. Inprocess step 752, a contact etch stopping layer (CESL) is deposited.This deposition may be performed via a chemical vapor deposition (CVD)process. In process step 754, a portion of the CESL is removed, exposingthe upper portion of the stressor regions. In process step 756, asilicon oxide layer is deposited on the structure, including on thestressor regions. In process step 758, a flowable oxide is deposited. Inprocess step 760, an anneal, such as a steam anneal, is performed.

FIG. 8 is a flowchart 800 indicating process steps for alternativeillustrative embodiments. In process step 850, stressor regions areformed. The stressor regions may include formation of regions of silicongermanium (SiGe), silicon phosphorous (SiP), and silicon carbonphosphorous (SiCP). The stressor regions may be formed via an epitaxialprocess. In process step 852, a silicon layer is deposited on thestructure, including on the stressor regions. In process step 854, aflowable oxide is deposited. In process step 856, an anneal, such as asteam anneal, is performed. As a result of process steps 854 and 856,the silicon deposited over stressor regions in process step 852oxidizes, forming a silicon oxide layer that protects the stressorregions formed in process step 850.

As can now be appreciated, embodiments of the present invention provideimproved fabrication methods for field effect transistors, such asfinFETs. By protecting the stressor regions, the imparted stress ismaximized, which increases carrier mobility, thereby improving deviceperformance.

While the invention has been particularly shown and described inconjunction with exemplary embodiments, it will be appreciated thatvariations and modifications will occur to those skilled in the art. Forexample, although the illustrative embodiments are described herein as aseries of acts or events, it will be appreciated that the presentinvention is not limited by the illustrated ordering of such acts orevents unless specifically stated. Some acts may occur in differentorders and/or concurrently with other acts or events apart from thoseillustrated and/or described herein, in accordance with the invention.In addition, not all illustrated steps may be required to implement amethodology in accordance with the present invention. Furthermore, themethods according to the present invention may be implemented inassociation with the formation and/or processing of structuresillustrated and described herein as well as in association with otherstructures not illustrated. Therefore, it is to be understood that theappended claims are intended to cover all such modifications and changesthat fall within the true spirit of the invention.

1.-20. (canceled)
 21. A semiconductor structure, comprising: a gate; aplurality of stressor regions adjacent to the gate; a contact etchstopping layer disposed on at least a part of each at least one sideportion of the gate and at least one side portion of each of theplurality of stressor regions; and a silicon oxide layer disposed on thegate and plurality of stressor regions.
 22. The semiconductor substrateof claim 21, wherein the contact etch stopping layer comprises siliconnitride.
 23. The semiconductor substrate of claim 21, wherein thesilicon oxide layer has a thickness ranging from about 50 angstroms toabout 150 angstroms.
 24. The semiconductor substrate of claim 21,wherein the plurality of stressor regions comprise a silicon germaniumregion.
 25. The semiconductor substrate of claim 21, wherein theplurality of stressor regions comprise a silicon phosphorous region. 26.The semiconductor substrate of claim 21, further comprising a spacerlayer disposed on at least a part of each at least one side portion ofthe gate.
 27. The semiconductor substrate of claim 26, wherein thespacer layer comprises silicon nitride.
 28. The semiconductor substrateof claim 21, further comprising a pad nitride layer disposed over thegate.
 29. A semiconductor structure, comprising: a gate; a plurality ofstressor regions adjacent to the gate; a silicon oxide layer disposed onthe gate and plurality of stressor regions; and a flowable oxidedisposed on the plurality of stressor regions
 30. The semiconductorsubstrate of claim 29, wherein the silicon oxide layer has a thicknessranging from about 10 angstroms to about 50 angstroms.
 31. Thesemiconductor substrate of claim 29, wherein the plurality of stressorregions comprise a silicon germanium region.
 32. The semiconductorsubstrate of claim 29, wherein the plurality of stressor regionscomprise a silicon phosphorous region.
 33. The semiconductor substrateof claim 29, further comprising a spacer layer disposed on at least apart of each at least one side portion of the gate.
 34. Thesemiconductor substrate of claim 33, wherein the spacer layer comprisessilicon nitride.
 35. The semiconductor substrate of claim 29, furthercomprising a pad nitride layer disposed over the gate.